At advanced nodes and in the most advanced packages, physics is no one’s friend. Escalating density, smaller features, and thinner dies make it more difficult to dissipate heat, and they increase mechanical stress. On the flip side, thinner dielectrics and tighter spaces make it more difficult to insulate and protect against that heat, and in conjunction with those smaller features and higher density, it makes them more prone to failure due to thermal runaway or accelerated aging.

This becomes even more complicated in heterogeneous designs, where different combinations of materials with varying coefficients of thermal expansion can result in die shift, warpage, and failure to make connections between die. That, in turn, can affect performance and power. Consequently, rather than just relying on the silicon substrate to remove the heat in a planar device at established process nodes, thermal effects need to be identified early, analyzed, and then addressed.

“Co-planarity and warpage are key concerns as we assemble multiple chips — sometimes 7 to 12 on a single organic substrate,” said Ingu Yin Chang, senior vice president at ASE Group. “Localized thermal management is also a concern, because a certain area will have hotspots. That’s something we are working on with our suppliers or customers to identify in the early stages so that we know what to do in terms of overall thermal management.”

These kinds of problems are cropping up everywhere, from PCBs — which are becoming increasingly dense, as well — all the way into the most advanced packages. Consider copper balance, for example, which is a way to symmetrically distribute copper traces in every layer of the PCB stack. Chip Greely, vice president of engineering at Promex, said that balance is necessary to avoid board twisting, bowing, or warpage. While copper balance was defined decades ago at the board level, it now has made its way to the chip level. “Copper balance has turned into a problem at the individual package level, where I’m putting in 7, 10, or 12 different devices, flipping them, or die-attaching them onto a substrate at different temperatures.”

Read more: Managing Thermal-Induced Stress In Chips