In the illuminating exploration titled “Die-Level Thinning And Integrating Route For Singulated MPW Chips Using Both Silicon Sensors And CMOS Devices” on Semiconductor Engineering.
The demand for ultra-thin silicon devices is surging across various applications, with flexible electronics standing at the forefront. To meet this demand, delves into a groundbreaking post-processing method that focuses on two silicon devices: an electrochemical impedance sensor and Complementary Metal Oxide Semiconductor (CMOS) die. Both these devices are sourced from a multi-project wafer (MPW) batch, and masterfully thins them at the die-level post dicing, ultimately reducing their thickness to an impressive 60 µm.
These finely thinned dies undergo a transformation, being flip-chip bonded to flexible substrates and hermetically sealed. The sealing is accomplished through two techniques: thermosonic bonding of Au stud bumps and anisotropic conductive paste (ACP) bonding. This strategic approach ensures that the thinned dies are not only compact but also possess impeccable reliability.
The thinned sensors are compared to their original counterparts, revealing advancements in both miniaturization and functionality. Importantly, the flip-chip bonded thinned sensors exhibit long-term reliability surpassing that of conventional wire-bonded sensors, underscoring the potential for game-changing innovations.
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Article with all rights reserved, courtesy of Semiconductor Engineering